1. Technical Field
This invention relates generally to semiconductor devices, and more particularly, to the configuration of high-power input/output semiconductor devices.
2. Background Art
FIGS. 1 and 2 illustrate a portion of a typical high-power input/output silicon-on-insulator (SOI) structure 20 of a semiconductor device, which structure communicates with core transistors on the same chip, and the input/output structures of one or more other chips. As is well known, the structure includes an oxide layer 22 on a silicon substrate 24, the oxide layer 22 having a silicon layer 26 thereon. Formed in the silicon layer 26, and properly isolated by silicon trench isolation oxide 28, are a number of large, elongated N channel and P channel transistors, in this typical embodiment (reading from left to right in FIGS. 1 and 2) electrostatic discharge, i.e., ESD-protection N channel transistors 30, 32, P channel transistor 34, P channel transistor 36, N channel transistor 38, N channel transistor 40, P channel transistor 42, P cannel transistor 44 (all operative input/output transistors), and ESD-protection N channel transistors 46, 48 in successive side-by-side, laterally spaced relation as shown, for which to the order is EE PP NN PP EE wherein E represents an ESD-protection N channel transistor, P represents a P channel transistor, and N represents a non-ESD-protection N channel transistor, for which the minimum periodicity for non-ESD-protection N channel transistors is 1, the minimum periodicity for P channel transistors is also 1, and the proportion of ESD-protection N channel transistors to the total number of transistors is 4/10.
Each transistor includes a source, a drain, and a gate above the transistor channel (for example transistor 30 includes source 50, drain 52 and gate 54). As is well-known, electron mobility is substantially greater in N channel transistors than hole mobility in P channel transistors. This results in substantially higher current (and substantially higher specific heat density) in an N channel transistor that in a P charnel transistor of similar size. Thus, typical designs provide greater “length” of P channel transistors to commute for the mobility difference.
While the advantages of an SOI device in semiconductor technology are well known (for example, maximizing speed, minimizing current leakage and capacitance and eliminating latchup problems), the high thermal impedance oxide layer 22 between the transistors 3048 and the silicon substrate 24 (from which heat is removed from the overall structure) can impede heat flow from the transistors to the substrate 24. While this is not a significant problem for the ES) protection N channel transistors 30, 32, 46, 48, which only operate for a very short period of time during a current spike, or the (lower current) P channel transistors 34, 36, 42, 44, the conventional, i.e., non ESD-protection N channel transistors 38, 40, grouped in successive adjacent relation as is shown in the typical structure of FIGS. 1 and 2, can cause significant heat buildup. This heat buildup can greatly increase current leakage and decrease mobility, degrading transistor performance, in extreme cases causing transistor failure.
Therefore, what is needed is a high-power input/output SOI semiconductor structure which includes transistors of various types laid out in a manner so as to avoid problems of heat buildup, taking advantage of silicon's (or other semiconductor material) high thermal conductivity and low spreading resistance.